The present invention is related to CPUs (Computer Processor Units) having a cache memory and, in particular, to cache memory controllers and their method of operation.
In an effort to speed access to memory information, many computer systems have a cache memory which is closely coupled to the CPU. The cache memory is formed from high-speed memory cells, which allow the CPU unit to have quicker access to the requested information than the slower, but less expensive, main memory. For example, many personal computer systems today have a cache memory of static RAM (Random Access Memory) cells with a main memory of slower dynamic RAM cells.
The main memory is much larger than the cache memory. At any time the cache memory holds only a fraction of the contents of the main memory. Thus the cache memory replaces its contents with information from the main memory to remain current with the requests from the CPU. A cache controller unit in the computer system handles the CPU requests to determine the requested information is in the cache memory, a "hit", or not, a "miss". If there is a hit, the cache memory supplies the information to the CPU. If there is a miss, the cache controller refills the cache memory with the requested information. The information is then transferred from the cache memory to the CPU.
Misses and the resulting cache refill operation slow the operation of the CPU, which must wait for the requested information. To avoid misses and the subsequent refill operation, information which will be used by the CPU should be kept in the cache. Of course, predicting the future is difficult so various techniques are used to keep the limited amount of cache memory filled with information which is likely to be used by the CPU. For example, when a miss occurs and information in the cache memory must be replaced to make room for the requested information, the common Least Recently Used algorithm technique discards the information which was last used by the CPU the farthest back in time, as the name implies. Based upon the fair assumption that a CPU continues to request the same information most of the time, this technique increases the likelihood of a hit.
On the other hand, the present invention assumes a refill operation and provides for improvements to the cache controller and the refill operation so that the operation of the CPU is retarded as little as possible.